Semiconductor memory devices are typically classified into volatile memory devices and non-volatile memory devices. Volatile memory devices are subdivided into dynamic random access memories (DRAMs) and static random access memories (SRAMs). Non-volatile memory types include mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs). Additionally, flash EEPROMs are advantageous as mass storage devices because their integration density is high compared with conventional EEPROMs.
Non-volatile semiconductor memories have attained broad utilization due to an ability to retain data within a device, even after power has been suspended. EEPROMs are non-volatile semiconductor memories that possess these abilities and additionally are able to store data by electrically erasing and writing storage devices. This programming process can be repeated over hundreds of thousands of cycles.
A flash memory is a type of non-volatile memory where all bit cells or pages of bit cells are erased simultaneously to a logic one or logic zero level before programming occurs. A bit cell is programmed by hot electron injection (HEI). Each bit cell of the flash memory is erased by tunneling of electrons through a thin tunnel diode window from a conductive channel to a floating polysilicon gate. The bit cell contains a select transistor and a sense or memory transistor. With an NMOSFET device used for the memory transistor, erasure produces a logic level of “1” in the cell. A PMOSFET memory transistor produces a complementary result.
A charge pump is used for generating the voltages required for programming the bit cells of the flash memory. The size of a charge pump on a substrate is large due to the size of a typical capacitor used and the number of stages of capacitors required. It is desirable to keep the number of charge pumps per byte small in order to save space on the substrate due to the relatively large size of each charge pump.
Programming of a bit cell takes one programming time, tp. A charge pump programs one bit cell at a time. For the NMOSFET-type memory device, programming (writing) each bit cell involves setting the cell to a “0” logic level by biasing the cell with a charge pump and inducing hot electron injection for the programming time, tp. In a bit cell to be programmed to a logic level “1,” no programming is required. The initial bulk erasing operation places each bit cell into a “1” logic level condition by default.
One or more charge pumps may engage a particular data structure. For instance, two charge pumps may be associated with a byte of data at a time. A total time for programming a data structure is given by
            BC      ×              t        P              CP    ,where BC is a number of bit cells in the data structure, tp is an amount of time for programming one bit cell, and CP is a number of charge pumps engaged in programming the data structure. For example, in the case of programming a single byte data structure with two charge pumps, the total programming time is equal to
      8    ×    3    ⁢                  ⁢    m    ⁢                  ⁢    sec    2or 12 milliseconds (msec) where the programming time, tp, for a single bit cell is 3 msec.
With reference to FIG. 1, a prior art process flow diagram 100 of a single charge pump programming a byte wide data structure commences with writing 110 Bit(7), where a bit cell index, i, equals 7. The process continues with writing 120 Bit(6) and continues through each bit position of the byte by decrementing the bit cell index, i, by one to engage each successive bit cell location. The process continues until reaching the step of writing 180 Bit(0). The process concludes with ending 190 the flow. The programming time for this process is 8×tp, where there are eight bit cells (BC=8) for the byte data structure and one charge pump (CP=1).
With reference to FIG. 2, a prior art process flow diagram 200 for two charge pumps programming a byte wide data structure commences with writing 210 Bits(7, 6), where a bit cell pair index, i:j, equals 7, 6. The process continues with writing 220 Bits(5, 4) and continues through bit pairs of the byte by decrementing each element of the bit cell pair index by two. The process continues until reaching the step of writing 240 Bits(1, 0). The process concludes with ending 250 the flow. A programming time for the dual charge pump process, substituting the prior art values into the expression given supra, is
      8    ×          t      P        2or 4×tp.
However, the direct approach of the prior art of engaging the charge pumps to the data structure does not take into account any correlation of a logic level set by the initial erasing of the bit cells and a logic level to be programmed. A direct programming approach applies an equal programming time per bit cell regardless of the final logic level of programmed data. A device not taking into account a lack of required programming for one gender of input data is expending programming time with no effective programming transpiring. This lack of effective programming happens with each occurrence of an input data value equaling the erased logic level. It would be ideal if a device would take into account the gender of data to be programmed and skip the programming of bit cell locations with an erased logic level equal to the gender of data to be programmed. Combining data gender coordinated programming with an ability to engage multiple charge pumps would truncate overall programming time in proportion to the amount of data equal to the logic level of the erased bit cells.